Allo Documentation

Quick search

Getting Started

Installation

Tutorials

Getting Started
Vivado/Vitis HLS Backend

Deep Dive

Data Types and Type Casting
Template Kernels
Kernel Composition
IP Integration
PyTorch Integration
Equivalence Checking
Other Features

Backends

LLVM (CPU)
AMD Vitis HLS (FPGA)
RapidStream TAPA (FPGA)
Multi-Threaded Simulator (CPU)
AMD MLIR-AIE (AI Engine)

Developer Guide

Developer Setup
IR Builder Walkthrough
MLIR Translation Guide

Python API

Schedule Primitives
Data Types

Feature Details¶

Timing-based Profiling
Trace-based Profiling
User-Defined External Kernels

<Getting Started with MLIR-AIE

Timing-based Profiling>

© Copyright 2025, Allo Authors. Created using Sphinx 8.2.3.

Styled using the Piccolo Theme